This is a patent application based on a Japanese patent application No. 2000-152991 which was filed on May 24, 2000 and which is incorporated herein by reference.
1. Field of the Invention
The present invention relates to a method for manufacturing a light-emitting device (LED, LD, etc.) using a group III nitride compound semiconductor, which has a multiple quantum well (MQW) structure.
2. Description of the Related Art
A conventional method for manufacturing a light-emitting device using a group III nitride compound semiconductor and a quantum well structure, comprises the steps of forming a well layer; forming a cap layer, whose band gap is wider than that of the well layer and whose band gap is the same as or narrower than that of the barrier layer at the same temperature at which the well layer is formed; removing the cap layer by thermal cracking (or decomposition) caused by raising the temperature of the substrate at which the barrier layer is formed; and forming a barrier layer on the well layer is well known.
One goal of this conventional method was to prevent the well layer from subliming during the barrier layer formation and thereby both prevent an unnecessary luminous center and improve luminous efficiency. Because sublimation of the well layer can be prevented and the barrier layer can be formed on the well layer by utilizing this conventional method, each well layer typically has an uniform thickness, which enables the well layers to maintain excellent crystallinity.
In fact, this conventional method can more than double the luminous efficiency of the semiconductor LED of a group III nitride compound semiconductor light-emitting device manufactured using earlier manufacturing methods at similar wavelength under equivalent driving voltage and electric current conditions.
However, problems remain in the application of the conventional method. Specifically, in order to form a cap layer which has both a wider band gap than a well layer and the same or a narrower band gap than a barrier layer in the conventional LED, the well layer and the cap layer generally comprise semiconductor layers of quite different composition. These compositions differences result in severe concentration gradients for some components such as indium (In) at the boundary region between the well layer and the cap layer in the conventional device. Futher, because of this severe concentration gradient, some portion of the components present in comparatively high concentration, e.g., indium (In), will diffuse into the adjacent lower concentration region when the substrate temperature is raised during formation of the cap layer and/or the barrier layer. This diffusion prevents the formation of a well layer near an interface between the well layer and the cap layer that exhibits the most desirable composition and crystallinity.
These difficulties associated with the convention process made it difficult to form a satisfactory steep hetero interface between the well layer and the barrier layer in a conventional LED. As a result, the conventional LED could not obtain an efficient luminous efficiency.
Accordingly, in light of the above problems, an object of the present invention is to form a well layer having a high degree of crystallinity and thereby to obtain a light-emitting semiconductor device (such as an LED or a laser) having high luminous efficiency by preventing exchange and diffusion of semiconductor components, e.g., indium (In), existing between the well layer (emission layer) and the cap layer during the process of forming the cap layer or during subsequent high temperature processes.
In order to achieve above object, a first aspect of the present invention is a method for manufacturing a LED, which uses group III nitride compound semiconductor and has a quantum well structure, comprising: forming a well layer; forming a cap layer on the well layer which has almost the same compositions as the well layer and comprising group III nitride compound semiconductor around the temperature at which the well layer is formed and at growth rate v ( greater than u) which is faster than crystal growth rate u of the well layer; eliminating at least a portion of the cap layer by using thermal cracking (or thermal decomposition) during a thermal process during which the temperature is raised for forming a subsequent group III nitride compound semiconductor layer; and forming the group III nitride compound semiconductor layer. Here composition of the cap layer may be identical to the composition of the well layer.
A second aspect of the present invention is to adjust the growth rate v of the cap layer to be about 1.5 times to 5 times larger than the crystal growth rate u of the well layer.
A third aspect of the present invention is to form the well layer using Al(1xe2x88x92x1xe2x88x92y1)Gay1Inx1N (where 0.05xe2x89xa6x1xe2x89xa60.50, 0xe2x89xa6y1, x1+y1xe2x89xa61). For example, Gay1Inx1N (x1+y1=1) and Al(1xe2x88x92x1xe2x88x92y1)Inx1N (y1=0) properly are included.
A fourth aspect of the present invention is to form the well layer using Ga(1xe2x88x92x1)Inx1N (where 0.05xe2x89xa6x1xe2x89xa60.50).
A fifth aspect of the present invention is to form the cap layer using Al(1xe2x88x92x2xe2x88x92y2)Gay2Inx2N (where 0.07xe2x89xa6x2xe2x89xa60.60, 0xe2x89xa6y2, x2+y2xe2x89xa61).
A sixth aspect of the present invention is to form the cap layer using Ga(1xe2x88x92x2)Inx2N (where 0.07xe2x89xa6x2xe2x89xa60.60).
A seventh aspect of the present invention is to adjust indium composition ratio x2 of the cap layer to be larger than indium composition ratio x1 of the well layer.
An eighth aspect of the present invention is to form a cap layer having a porous structure in which the atomic vacancies are scattered.
A ninth aspect of the present invention is to form a cap layer having a thickness which is completed to be eliminated till the next layer of the group III nitride group compound semiconductor is started to be formed.
A tenth aspect of the present invention is to adjust the growth rate v of the cap layer to be more than 10 xc3x85/min.
An eleventh aspect of the present invention is to adjust the growth rate v of the cap layer to be in a range of 15 xc3x85/min. to 30 xc3x85/min.